Field of the Invention:
This invention relates generally to semiconductor memory circuits, and particularly to circuits and methods for repairing semiconductor memory circuits having redundant memory cells.
Semiconductor memories generally include a multitude of memory cells arranged in rows and columns. Each memory cell is structured for storing digital information in the form of a “1” or a “0” bit. Many semiconductor memories include extra, i.e., redundant, memory cells that may be substituted for failing memory cells. Semiconductor memories are typically tested after they are fabricated to determine if they contain any failing memory cells (i.e., cells to which bits cannot be dependably written or from which bits cannot be dependably read). Generally, when a semiconductor memory is found to contain failing memory cells, an attempt is made to repair the memory by replacing the failing memory cells with redundant memory cells provided in redundant rows or redundant columns in the semiconductor memory array.
Conventionally, when a redundant row is used to repair a semiconductor memory containing a failing memory cell, the failing cell's row address is permanently stored (typically in pre-decoded form) by programming nonvolatile elements (e.g., fuses, antifuses, Electrically Programmable Read-Only memory (EPROM), and FLASH memory cells) on the semiconductor memory. Then, during normal operation of the semiconductor memory, if the memory's addressing circuitry receives a memory address, including a row address that corresponds to the row address stored on the chip, redundant circuitry in the memory causes access to a redundant row instead of the row identified by the received memory address. Since every memory cell in the failing cell's row has the same row address, the redundant row replaces every cell in the failing cell's row, both operative and failing, with the redundant memory cells in the redundant row.
Similarly, when a redundant column is used to repair the semiconductor memory, the failing cell's column address is permanently stored (typically in pre-decoded form) on the chip by programming nonvolatile elements on the chip. Then, during normal operation of the semiconductor memory, if the memory's addressing circuitry receives a memory address, including a column address that corresponds to the column address stored on the chip, redundant circuitry in the memory causes a redundant memory cell in the redundant column to be accessed instead of the memory cell identified by the received memory address. Since every memory cell in the failing cell's column has the same column address, every cell in the failing cell's column, both operative and failing, is replaced by a redundant memory cell in the redundant column. This process for repairing a semiconductor memory using redundant rows and columns is well known in the art.
A typical semiconductor memory may have many redundant rows and many redundant columns, each redundant block (whether for a row or column) including its own nonvolatile programming elements for enabling and programming the address to which it will respond. As feature sizes on semiconductor devices continue to shrink, the density of memory cells on a semiconductor die continues to increase, allowing more memory cells on a semiconductor die, which in turn require more redundant rows and columns to repair the increased number of memory cells. Because of an increased number of redundant rows and columns, an increased number of nonvolatile elements are required to select each redundant row and each redundant column. Unfortunately, sizes for nonvolatile programming elements have not reduced proportionately to size reduction for memory cells. As a result, the nonvolatile programming elements take up a larger portion of the available semiconductor die area. In some designs, the nonvolatile programming elements may take up as much as five to ten percent of the overall semiconductor die area.
It would be advantageous to provide an apparatus and method using a reduced number of nonvolatile programming elements associated with repairing a semiconductor device, without compromising overall ability to perform repairs or impact operational speed while reducing area requirements for supporting selection of redundant rows and redundant columns on a semiconductor memory device. Further, it would be advantageous to reduce power use and reduce loading on address signals used to select redundant rows and columns.